The present invention relates to a semiconductor memory device and, more particularly, to a circuit and a method for performing a clock training in order to align a data transfer between an apparatus having a high speed data processing function and a semiconductor memory device.
In a system including a plurality of semiconductor devices, the semiconductor memory device stores data. When a data processing unit, i.e., a CPU, requires data, the semiconductor memory device outputs data corresponding to an address inputted from the data processing unit or stores data provided from the data processing unit in a cell position corresponding to the address.
With the increase in the operation speed of a system having semiconductor devices and the development of a technology regarding a semiconductor integrated circuit, the semiconductor memory device is required to output or store data faster than before. In order to input/output data in a high speed, a synchronous memory device, which is capable of inputting/outputting data in synchronization with a system clock inputted from the outside, has been developed. However, since the synchronous memory device does not sufficiently satisfy the required speed of inputting/outputting data, a DDR (Double Data Rate) synchronous memory device, which is capable of inputting/outputting data at a rising edge and a falling edge of a system clock, respectively, has been developed.
Since the DDR synchronous memory device should input/output data at the rising edge and the falling edge of the system clock, respectively, it should process two data within one time period of the system clock. That is, the DDR synchronous memory device should output data or receive and store data at the rising edge and the falling edge of the system clock, respectively. Particularly, a timing at which the DDR synchronous memory device outputs data should accurately synchronize with the rising edge or the falling edge of the system clock. Thus, a data output circuit within the DDR synchronous memory device is used to control an internal output and a transfer timing of data so that the data are in synchronization with the rising edge and the falling edge of the inputted system clock to be outputted.
Recently, in the semiconductor memory device capable of processing large-capacity data faster, the input/output speed of an address as well as data is increased. In the conventional semiconductor memory device, the address is in synchronization with a rising edge of a clock along with an external operation command to be inputted. That is, the conventional semiconductor memory device receives the address and the operation command inputted from the outside once per period of the external clock (namely, in response to the rising edge) to perform an internal operation. However, with the increase in the operation speed of the semiconductor memory device, a structure in which the semiconductor memory device receives the address not once but twice is suggested.
A GDDR5 (Graphics Double Data Rate version 5) semiconductor memory device for a graphics operation is designed to receive the address at the falling edge as well as the rising edge of the external clock. Since the GDDR5 semiconductor memory device can receive the address twice within one period, the number of address pins is reduced as compared with the conventional semiconductor memory device and remaining address pins are connected to a power supply voltage or a ground voltage so that the operation speed of the semiconductor memory device can be increased. Since the operation command inputted from the outside is still inputted in response to the rising edge of the external clock, the input speed of an address signal becomes twice as fast as the input speed of the operation command, and the large-capacity semiconductor memory device can be supported in a high speed.
Also, the GDDR5 semiconductor memory device inputs/outputs two data between the rising edge and the falling edge of the external clock and inputs/outputs two data between the falling edge and the next rising edge of the external clock. That is, the GDDR5 semiconductor memory device inputs/outputs four data within one period of the external clock.
The high-speed semiconductor memory device uses, as a reference clock, the system clock which is used for transferring and receiving the address and the command and a data clock which is used for inputting/outputting data. Here, the frequency of the data clock is twice as much as that of the system clock. That is, unlike the conventional semiconductor memory device which performs internal operations, such as a read or write operation, using one system clock as a reference, the high-speed semiconductor memory device and the data processing unit use two clocks having different frequencies to exchange data. However, if the phases of the system clock and the data clock are not aligned, the reference signal for transferring the command and the address and the reference signal for transferring data are not aligned, that is, the semiconductor memory device cannot normally operate. Therefore, an interface training between the semiconductor memory device and the data processing unit is initially performed.
The interface training is performed to train an interface for transferring the command, the address and the data to operate at an optimized timing before a normal operation between the semiconductor memory device and the data processing unit is performed. The interface training includes an address training, a clock alignment training (or WCK2CK training), a read training and a write training. Particularly, in a system in which the clock used for the reference signal for transferring the command and the address and the clock used for the reference signal for transferring data exist separately, the clock alignment training is for aligning the data clock (WCK) with the system clock (CK) before the high-speed semiconductor memory device performs the read and write operations.